This software package provides several examples beside the source code for the UVM scoreboard. Before starting to integrate the UVM scoreboard into your own code, it might be beneficial to look at the provided examples. An example testbench is placed in the tb directory and the tests are in the tb/test directory.

To run the examples you need to select a Vendor since the examples can be run with all of the three major SystemVerilog simulator vendors: Cadence, Siemens EDA, and Synopsys. See README.txt for a description of how to select the vendor.

Once the vendor has been selected the available Make targets for that vendor can be listed by typing: "make". Typically, you run the simulation with make sim.

In general you can type make help to get information about the Make options that are available.